FPGA延时/面积最小化工艺映射分层序列法

THE TIMING/AREA OPTIMIZATION ALGORITHM FOR LUT BASED FPGA TECHNOLOGY MAPPING

摘要: 提出了一个求解FPGA延时/面积最小化工艺映射分层序列法。它首先给出了求解延时最小化工艺映射的步骤；然后在不增加延时的情况下，进行面积最小化．

Abstract: This paper presents a performance-driven technology mapping algorithm. Firstly, it gives a technology mapping algorithm for delay minimization. And then, it gives a area optimization algorithm without increasing delay.