Abstract: The increasing test data volume and test power are two major problems in testing system-on-a-chip. This paper proposes a scan chain reconfiguration algorithm named Run-Reduced-Reconfiguration (3R).Without impacting normal functions of the chip,the 3R algorithm reconfigures scan chains by reordering chains and adjusting cells' polarities to reduce the number of runs in order to improve test compression ratio and reduce test power. Also,the paper discusses the trade-off between compression ratio and scan chain wire length. The experimental results show that after executing 3R algorithm the compression ratio is improved by 52% and the scan power is reduced by 53%.