Abstract: With the development of deep sub-micron VLSI design‚the behavior of parasitic RCs derived from substrate and inter-connection becomes key factor of affecting circuit speed and signal integrity.Generally‚the extracted RCs constitute a very large scale network that needs reduction to fit for efficient timing analysis.Several important modifications have been made to the classic RC network reduction algorithm PACT that significantly improved the performance of network reduction.At the same time‚the algorithm overcame the limitation of the classic PACT algorithm‚being capable of handling the internal nodes without any DC path to ports of the RC netlist.Computation results show that the modified algorithm is several times faster than the classic PACT algorithm without losing any computational accuracy.