Abstract: Dummy fill insertion for chemical mechanical polishing (CMP) enhances the planarization of wafer surface.However,it causes significantly varying impact on the circuit performance.A performance aware dummy fill insertion algorithm for reducing the coupling effects on critical nets is presented.First,sweep line algorithm is used to find fill regions of each tile on the layout.Secondly,the fill regions are classified according to the criticality of the surrounding net segments.Then the fill amount of each fill region is reassigned based on its class.Finally,analytical hourglass-shape fill patterns are inserted in each fill region.Experimental results show that the proposed algorithm can reduce the delay of net by 15% on average than the traditional algorithm.