Abstract: A serial feedback- based scheme for built-in at-speed self-test is proposed in this paper. By using on-chip feedback lines to link PRPG and MISR, aliasing can be reduced, compared to a conventional output register MISR. The analysis of State Transition Graph (STG) topology reveals that it is possible to design a serial feedback-based BIST structure yielding STGs of disjunct rings only. If a large ring is found, it will be a candidate for a test sequence leading to a high fault coverage.