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嵌入式处理器在片调试功能的设计与实现

Design and Implementation of On-chip Debug Features in Embedded Processor

  • 摘要: 以龙芯1号处理器为研究对象,探讨了嵌入式处理器中在片调试功能的设计实现方法.通过扩充IEEEP1149.1协议的JTAG测试访问端口(TAP),并在处理器内部增加控制模块,实现了软件调试断点、调试中断、硬件断点以及单步执行等多种在片调试功能.调试主机只需要通过一根JTAG调试电缆就可以访问目标处理器内部寄存器等各种资源,并控制目标处理器的运行过程,实现了处理器的在片调试功能,大大地方便了软件开发与系统调试.

     

    Abstract: With Godson-1processor as the research prototype,a design scheme of on-chip debug features in embedded processor is presented in this paper.In the scheme the IEEE P1149.1JTAG TAP module is extended and some control logic is added inside the processor core to provide the following new capabilities for software and system debug:software debug breakpoint,debug interrupt,hardw are breakpoint,singlestep execution,etc.With only a JTAG debug cable,the debug host can access the internal resources and control the program running of the processor under debug.With the se on-chip debug features,the software development and system debug are facilitated greatly.

     

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