Abstract: A fast fault simulator (P+P) for synchronous sequential circuits is developed. P+P uses parallel patterns and parallel faults algorithm. Two way parallelism for synchronous sequential circuit fault simulation is realized. Some new techniques, such as global fault grouping, circuit levelization, cone operation, and improved ID etc. are applied. P+P is realized on SUN SPARC 2 with random patterns, and runs on most of the ISCAS benchmark circuits. Experiment results are given in the last.