以延时优化为目标的工艺映射驱动的分解方法
THE MAPPING-DRIVEN DECOMPOSITION FOR DELAY MINIMIZATION
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摘要: 逻辑电路的分解影响FPGA工艺映射后目标电路的延迟时间,采用何种分解方式也与映射结果密切相关。为快速有效地缩短电路延时,本文从工艺映射的基础理论出发,提出映射驱动的逻辑分解方法。Abstract: The decomposition of the logic circuits can minimize the delay of the FPGA technology mapping solutions.How to decompose the logic circuits is also related to the mapping results.To shorten the final mapped circuits rapidly and effectively,a new algorithm called the mapping-driven decomposition is presented in this paper.It is based on the basic theory of the FPGA technology mapping.
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