Abstract: A new fault simulation approach to combinational circuits is proposed in this paper. For a given input vector, the true-value simulation, which is used to compute signal values of each line, is performed from primary inputs(PI)towards primary output (PO) as usual, but the fault simulation is done by expression operation in the descending order of logic level from PO to PI. Whether it detects the single fault s-a-0 or s-a-1 on every line can be decided from the expression. An algorithm that combines this approach with critical path tracing (CPT) is also introduced and it simplifies the processing procedure of the criticality computing of fanout stems in CPT.