Abstract: With the wide application of System-on-Chip in embedded system design,the hardwaresoftware partitioning turns from a traditional bipartition problem to a mult-i way partitioning problem. To deal with this issue,an abstract template of the processing element network connecting with communication channels is proposed for modeling multiple processing module architecture.Simulated annealing and heuristic scheduling algorithms are employed to determine the mult-i way hardware-software partition and estimate the system performance and cost respectively.Preliminary experiments show that the proposed algorithm can make reasonable choice among different architectures for the optimization of system performance and cost.