Abstract: A two-dimensional test data compression scheme for System-On-a-Chip (SOC) is proposed. By utilizing the technique of LFSR reseeding, the test patterns with unspecified bits are first compressed, and then the seed difference sequences obtained are further compressed with Golomb codes. In the meantime, determination of the Golomb code parameter m and the corresponding two-dimensional decompression architecture is also given. Experimental results show that the scheme, under the precondition of ensuring higher fault coverage,not only reduces the length of test sequences and shortens test time, but also lowers effectively the requirement for test data bandwidth.