基于改进的Voronoi图划分的边界元衬底耦合参数提取技术

Modified Voronoi Diagram Layout Partition Based Substrate Coupling Parameter Extraction Technique Using BEM

摘要: 提出了一种快速而准确的数模混合集成电路衬底耦合参数提取方法.采用边界元法求解衬底耦合电阻,与有限差分法相比,计算速度提高了一个数量级以上,且可以保持精度.结合改进的Voronoi图来划分版图,生成的衬底RC网络数目远小于同样采用Voronoi图的文献4,而且解决了文献4中由于解析公式计算衬底电阻导致精度不高的问题.

Abstract: An efficient and accurate substrate coupling parameter extraction method for mixed signal IC is introduced.Boundary Element Method is used to compute substrate coupling resistance.Comparing to Finite Difference Method,the computing speed is improved more than one order,and the precision of the result is retained.Combined with layout partition based on modified Voronoi diagram,the scale of substrate RC network is far smaller than that reported in the literature4 where Voronoi diagram is used to partition the layout too.