Abstract: The hierarchical block boundary element method is highly efficient by its once computation to extract the whole interconnect capacitance matrix. In analog integrated circuit layout, the feature size varies largely with different layers. According to this, we present an improved algorithm in this paper, including a new hierarchical partition method of 3D blocks, nonuniform subdivision of boundary elements, and optimization of algorithm organization. Numerical results show that the new algorithm is suitable for real analog integrated circuit layout, in an improvement under equal accuracy, a few times faster than the previous approach.